The co-founder of Intel and Fairchild Semiconductors, Gordon Moore, made a famous observation in 1965 that the number of transistors in a chip would double every year. This became known as Moore’s Law, and it has been a guiding principle for the semiconductor industry ever since. However, Moore himself revised his prediction in the 1970s and said that the doubling would occur every two years instead. According to the current Intel CEO, Pat Gelsinger, the rate of doubling has further slowed down, and now it takes about three years for the transistor count to double.
The transistor count of a chip is a crucial factor that determines its performance and efficiency. For instance, the iPhone 11 series from 2019 used the 7nm A13 Bionic chip, which had 8.5 billion transistors in each unit. The iPhone 15 Pro and iPhone 15 Pro Max from 2023 use the 3nm A17 Pro chip, which has 19 billion transistors in each unit and delivers significant improvements in speed and power consumption over the A13 Bionic.
As reported by Tom’s Hardware, Gelsinger gave a talk at the Manufacturing@MIT symposium and claimed that Moore’s Law was “alive and well” and that Intel could beat the pace of Moore’s Law until 2031. Intel is expected to regain its process leadership from TSMC and Samsung Foundry with its A18 (1.8nm) process node in 2025, which will be smaller than the 2nm node that the other two foundries will use to produce cutting-edge chips in the same year. Gelsinger stated in his talk, “We have been announcing the demise of Moore’s Law for about three or four decades.” He acknowledged that “we are not in the golden age of Moore’s Law anymore; it is much, much more difficult now, so we are probably doubling effectively closer to every three years now, so we have definitely witnessed a slowdown.” Gelsinger proposed a “Super Moore’s Law” concept that relies on using 2.5D and 3D chip packaging to boost transistor counts. Gelsinger also called this “Moore’s Law 2.0.”
Gelsinger also predicted that by 2030, Intel could create a chip that would have one trillion transistors. He mentioned four things that could enable this feat, including RibbonFET transistors. These are similar to the Gate-All-Around transistors that Samsung Foundry uses for its 3nm production, where the gate surrounds the channel on all four sides, reducing current leakage and increasing drive current.
PowerVIA power delivery is another thing that could lead to a trillion-transistor chip. This technique places the power supply lines on the back of the chip instead of the front, enhancing power and performance. The third thing is the next-gen process nodes that will arrive in the next few years, which will shrink the size of transistors and allow more to fit in a chip. The fourth thing is 3D chip stacking, which involves connecting 16 or more integrated circuits vertically to function as a single chip.
Gelsinger also noted that the economics of the industry have changed lately. “A modern fab would have cost about $10 billion seven or eight years ago,” he said. “Now, it costs about $20 billion, so you have seen a different shift in the economics.”